Paolo M.

About Paolo M.

Experienced researcher and designer in the area of computer architecture and design automation for heterogeneous system-on-chip. Skilled RTL and high-level synthesis designer with knowledge of interconnect standards, such as AXI, on chip network communication, memory hierarchy, power management, processor pipeline and floating-point operators architecture. Deep understanding of the hardware-software interface, including experience with device driver and low-level software API for programming hardware accelerators in both ARM and RISC-V based systems.More than 5 years developing, testing and automating the design of complex systems deployed on FPGA integrating processor cores with domain specific accelerators for computer vision and machine learning. Experience with FPGA peripherals and I/O interfacing, including serial transceivers, Ethernet and DDR.

Experience

1. Senior Software Engineer

   Google

   Jun 2021 — Present · New York, NY, US

Education

• Conservatory of Music - L. Campiani in Mantova

  BA, Piano diploma

  2000 — 2007

• Alma Mater Studiorum – Università di Bologna

  BS, Electronic Engineering

  2005 — 2008

• Columbia University

  PhD, Computer Science

  2011 — 2017

• Politecnico di Torino

  MS, Electronic Engineering

  2008 — 2010