Pankaj Kumar

About Pankaj Kumar

Specialties:DFT planning and RTL insertion (OCCs, EDTs, SSN/SSH, IJTAG network, SIBs, general-purpose TDRs, Intest and Extest mode control, clock-gate (CGC) and reset controller, considerations for HIP and multiple synthesizable blocks, scan isolation, and synthesis hookups); ICL/PDL generation, extraction, and verification; SpyGlass DFT to identify DFT-related issues (e.g, clock and reset) early in the RTL phase; SCAN insertion (scan chains, wrapper cells, test points, and pipeline scan enable); ATPG for various kinds of fault models (e.g, stuck-at, at-speed); test coverage analysis; timing and no-timing gate-level simulations (GLS) of chain, scan, IJTAG, loopback, and continuity patterns and debug; feedback to back-end on timing issues; virtual testing (VT); silicon support and debug (scan diagnosis).EDA Tools, Languages & Scripting:Siemens: Tessent, TestKompress, FastScan, ModelSim, DFT AdvisorSynopsys: TetraMAX, VCS, DFTMAX, Verdi, SpyGlass DFTCadence: Xrun, Xcelium, NCSimHardware Languages: Verilog, VHDLScripting: Tcl, Perl, Sed, Awk

Experience

1. Senior Dft Engineer

   Intel

   May 2018 — Present · Bangalore, IN

Education

• Raj Narain College (R.N. College), Hajipur

  Bachelor of Science, Physics (Honours)

  1998 — 2002

• Anugrah Narayan (A.N.) College, Patna

  Master of Science, Electronics

  2003 — 2006

• Thapar Institute of Engineering & Technology

  Master of Technology, VLSI Design & CAD

  2008 — 2010