Pankaj Khandelwal
- Role
- Cadence
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Pankaj Khandelwal
I have been working on different aspects of low power design and verification for the…
Experience
Present
Skills
- Static Timing Analysis
- Ic
- Formal Verification
- Low-Power Design
- Rtl Design
- Vlsi
- Semiconductors
- Algorithms
- Physical Design
- Soc
- Verilog
- Signal Integrity
- Debugging
- Application-Specific Integrated Circuits (Asic)
- Asic
- Perl
- Eda
- Tcl
- Simulations
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