Pankaj Kadam

About Pankaj Kadam

A Verification Engineer- VLSI by profession and a VLSI autodidact from heart.• 5+ years of experience in IP/Subsystem/SoC Functional Verification, GLS Verification, Low Power Verification on 7nm, 10nm technology.• Expertise in System Verilog and UVM based Verification environment development,• Experience in GLS and Low Power Aware verification.• Experience with a processor validation, VIP integration and verification and SoC verification teams.• Good knowledge of ASIC Verification workflow for front end verification test plan and feature extraction. • Mastered and overhauled founded Plug and Play VIP for CoE requirement to train fresher.• Good exposure on protocols like AMBA AHB, PCIe, STF/STC, JTAG TAP.• Good exposure to tools like VCS, NCSim simulators, Verdi, Modelsim, Altera Quartus, MatLab. • Good knowledge of Linux, Shell scripting, TCL. If you want to talk more about VLSI design verification, protocols, programming languages and methodologies used, hit or just email at: k••••••••@gmail.com

Experience

1. Technical Team Lead

   Wipro

   Sep 2021 — Present · Bengaluru, IN

Education

• Dr. Babasaheb Ambedkar Technological University, Lonere

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

  2009 — 2013

• Vellore Institute of Technology

  Master of Technology - MTech, VLSI Design

  2014 — 2016

Skills

• Cadence
• Asic
• Tcl
• Vhdl
• Cadence Virtuoso
• Perl
• Ip Verification
• Modelsim
• C
• Uvm
• Matlab
• Systemverilog
• Vlsi Cad
• Rtl Design
• Verilog