Pankaj Dhalvaniya

About Pankaj Dhalvaniya

Good understanding and hands-on experience with RTL design methodology Well versed with Micro-architecture design, RTL coding with Verilog/System Verilog Have designed and implemented multiple IPs from architecture to implementation and proven the designs on Xilinx FPGAs Expertise in Design tools like Spyglass Lint, Design Compiler, Verdi, Jasper Gold, Xcelium Parallel Simulator, ViVado, Matlab, Xilinx ISE, Ltspice, Cadence Genus, CDC Strong knowledge in ASIC and FPGA Logic Synthesis, Timing Analysis, Timing closure and UPF (for ASIC) Hands on experience on Digital Signal Processing, CMDA based wireless Modem Designing and Navigation systems like GPS, GLONASS Familiarity with multiple simulators and debugging Strong knowledge in Bus architecture in Tilelink, AXI, AHB, APB and other customized serialprotocols Good technical hands on leader with an ability to guide junior engineers Have done multiple IP/SS integration tasks using automated scripts for large SoC semiconductor companies Strong programming skill in Perl/Tcl

Experience

1. Principal Engineer - Rtl Design

   Micron Technology

   Nov 2024 — Present · Bengaluru, IN

Education

• G.H.Patel College of Engineering and Technology

  Bachelor of Engineering (BEng), Electronics and Communication Engineering

  2006 — 2010

• DA-IICT

  Mtech, VLSI and embedded Systems

  2011 — 2013