Pankaj Chafekar

About Pankaj Chafekar

12 years of physical design experience in semiconductor Industry in Tech nodes ranging from 28nm till 3nm and counting.• Physical design implementation of high performance and high-density Designs like CPU/NPU/IOU etc.• Part of and have lead many PPA activities to achieve best in class PD implementation.• Holding reach knowledge of every aspect VLSI chip design like Floorplanning, Synthesis, Placement of multimillion Instance, Clock Tree Synthesis, Routing congested design, PDN/EMIR Analysis and fixing, Fixing Physical and logical DRCs & timing fixes during ECO phase.• Very good understanding of Time Analysis part of design in GHz range with resolving signal integrity & Noise issue. • Detail conceptual Knowledge of Low Power Physical Design Methodology.• Exposure with Industry Standard tools like FC, ICC, Prime Time, Design Complier, ICV, Calibre, Star-RCXT, Voltus, Redhawk.Specialties: Physical Design, STA, PPA activities, Physical Verification (DRC, LVS), Signal Integrity issues, Extraction, scripting language, Organizational activities etc.Soft Skills :• Self-motivated and passion to achieve new heights.• Strong problem-solving abilities, qualitative aptitude, eagerness to learn, strong grasping power.• Effective communication, Good presentation & time management skills.Love to explore myself in lightning fast changing Semiconductor World & Happy to be a part of designing future Technology.

Experience

1. Senior Staff Engineer

   Qualcomm

   Jul 2024 — Present · Bengaluru, IN

Education

• Indian Institute of Technology, Bombay

  Master of Technology (M.Tech.) in electronic system

  2011 — 2013

Skills

• Rtl Design
• Tcl Scripting
• C++
• Physical Design
• Static Timing Analysis
• Asic Design
• Application-Specific Integrated Circuits (Asic)
• Timing Closure
• C
• Programming
• Pearl Scriptimg
• Matlab