Ronak Pandya
Principal Physical Design Engineer at Micron Technology
- Role
- Principal Physical Design Engineer at Micron Technology
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ronak Pandya
Worked on Physical design of various Memory interface IP such as ONFI PHY, DDR3, DDR3/4, LPDDR4X, LPDDR4/4x, GDDR6, digital DLL and NAND IOE with various architecture and technology node 8/10/14nm Samsung, 28nm tsmc and 22FDSOI GF.
Experience
Principal Physical Design Engineer
Aug 2024 — Present · Bengaluru, IN
Principal Engineer
Education
Thapar Institute of Engineering & Technology
Master of Technology (MTech), VLSI Design
2014 — 2016
Government Engineering College Ajmer.
Bachelor of Technology (BTech), Electronics and Communications Engineering
2009 — 2013
Skills
- Cadence Virtuoso
- Systemc
- Vlsi
- Fpga
- Linux
- Systemverilog
- Python
- Microsoft Word
- Electronics
- Questasim 10.2a
- Powerpoint
- System Verilog
- Eda -Mge
- C
- Programming
- Vhdl
- Matlab
- Tcl-Tk
- Cadence Encounter
- Embedded Systems
- Verilog
- Tanner Eda
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