Palvi Shrigiri
- Role
- Astera Labs
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Palvi Shrigiri
Architecture, Microarchitecture, System Verilog RTL
Experience
Present
Education
Santa Clara University
Master's Degree, Electrical Engineering
2014 — 2016
Savitribai Phule Pune University
Bachelor's Degree, Electronics and Telecommunications
2010 — 2014
Skills
- Verilog
- Powerpoint
- System Verilog
- Equivalence Checking
- Testing
- Data Structures
- Windows
- Matlab
- Arm
- C
- Programming
- Teamwork
- Assertion Based Verification
- Synopsys Tools
- Digital Signal Processing
- Microcontrollers
- Computer Architecture
- Mentor Graphics Ic Studio
- Microsoft Office
- Vlsi
- Assembly Language
- Systemverilog
- Microsoft Word
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