Pallavi Mayekar
Senior Design Verification Engineer at Qualcomm
- Role
- Senior Design Verification Engineer at 高通
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
About Pallavi Mayekar
Highly motivated Design Verification Engineer with 6 years of experience in Power Management IC\'s and a Master\'s degree in Electrical Engineering.Programming Languages: SystemVerilog, UVM, Perl, and Python.Software Tools: Cadence Virtuoso, Altera\'s Quartus, Mentor Graphics, AutoCAD, Pspice, LTSpice, Autocad, PCB Express, Eagle.https://repository.rit.edu/cgi/viewcontent.cgi?article=11322 & context=theses
Experience
Senior Design Verification Engineer
Aug 2021 — Present · San Diego, CA, US
Education
Rochester Institute of Technology
Master's degree, Electrical Engineering
2016 — 2019
University of Mumbai
Bachelor's degree, Electronics engineering
2013 — 2016
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