Palash Khandale

About Palash Khandale

I build IPs that deliver first-pass silicon success and hold up in real-world SoCs with confidence and on-time execution.With 10 years of industry experience, I’ve spent about 7+ years in ASIC design and integration, contributing to multiple successful tape-outs across 3nm, 4nm, 5nm, and 7nm nodes. I’ve delivered IPs as large as 8mm², with a focus on clean integration, area optimisation, and design maturity.My work spans: • Microarchitecture ownership and spec contribution • RTL integration with Lint, CDC (including reconvergence), synthesis elaboration, and formal sign-offs • Debug support for SoC-level power-up and sequence validation • Pipelining and parameterisation efforts to optimise area and minimise DV/test-bench impact • Participation in post-silicon bring-up, with exposure to silicon bugs and system triageEarlier in my career, I spent 2.5 years in FPGA-based design and deployment, contributing to emulation and production workflows. As part of a USB-IF member organisation, I developed test and validation tools for USB and DisplayPort, including CDR blocks, LTSSM, and Type-C FSMs.My technical toolkit includes:Protocols – AXI, AHB, APB, I2C, SPISoC Design – MMCM-based clocking, Reset/Power sequencing, SoC interconnects, GDSCTools & Flows – SpyGlass, Vivado, CDC/RDC checks, UPF, synthesis, DFT integrationDebug – Logic Analyzer, DSO, I2C-heavy setups, ARM-ADC streamingBeyond execution, I actively mentor engineers transitioning into ASIC/FPGA roles—bridging the gap between academic skills and industry-readiness through real project insights and mindset shifts.If you’re passionate about robust RTL design, clean handoffs, or growing in the semiconductor domain—I’d be happy to connect.

Experience

1. Staff Engineer

   Arm

   Mar 2026 — Present · Bengaluru, IN

Education

• G. H. Raisoni Polytechnic Nagpur

  Diploma in Electronics & Telecommunication, Electrical and Electronics Engineering

  2009 — 2012

• St. Vincent Palloti College of Engineering and Technology, Wardha Road

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2012 — 2015

Skills

• Matlab
• System Architecture
• Market Analysis
• Fpga
• Asic
• System on a Chip (Soc)
• Research
• Linux
• Field-Programmable Gate Arrays (Fpga)
• Vhdl
• C++
• Ip
• Shell Scripting
• Electronics
• Parasitic Extraction
• Soc
• Verilog
• Systemverilog
• Cmos
• Perl
• C
• Microsoft Office
• Zynq Soc