Paidi Revanth
Layout Design Engineer @KriSemi Design Technologies
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WORK HISTORY
Layout Design Engineer @KriSemi Design Technologies
Hyderabad, IN
EDUCATION
Pragati Engineering College
Bachelor of Technology - BTech
ABOUT PAIDI REVANTH
3.2 year of experience in Layout design.* Worked at Qualcomm, AMD as contractor.*Trained as an Memory Layout engineer at Inohmic training platform.* Good knowledge on layout verification DRC, LVS, ERC and Softcheck.* Good understanding on Antenna effect, Electromigration, IR-drop, Latchup.* Good knowledge on CMOS Fabrication process.* Device matching, Fingering, Shielding, LOD effects, WPE & STI.* Good communication skills and has the ability to work independently or as a team.* Schematics and layouts for Logic Gates like INV, NAND, NOR, AND, OR, XOR, XNOR etc.* Good understanding on Stick Diagrams.* Tools- Cadence virtuoso, Glade, LT Spice, Synopsys, Calibre.* Technology- TSMC 2nm, TSMC 3nm, TSMC 4nm, TSMC 20nm, TSMC & Custom_compiler 22nm.
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