Paidi Revanth
Layout Design engineer
- Role
- Layout Design Engineer at KriSemi Design Technologies
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Paidi Revanth
3.2 year of experience in Layout design.* Worked at Qualcomm, AMD as contractor.*Trained as an Memory Layout engineer at Inohmic training platform.* Good knowledge on layout verification DRC, LVS, ERC and Softcheck.* Good understanding on Antenna effect, Electromigration, IR-drop, Latchup.* Good knowledge on CMOS Fabrication process.* Device matching, Fingering, Shielding, LOD effects, WPE & STI.* Good communication skills and has the ability to work independently or as a team.* Schematics and layouts for Logic Gates like INV, NAND, NOR, AND, OR, XOR, XNOR etc.* Good understanding on Stick Diagrams.* Tools- Cadence virtuoso, Glade, LT Spice, Synopsys, Calibre.* Technology- TSMC 2nm, TSMC 3nm, TSMC 4nm, TSMC 20nm, TSMC & Custom_compiler 22nm.
Experience
Layout Design Engineer
Dec 2023 — Present · Hyderabad, IN
Education
Pragati Engineering College
Bachelor of Technology - BTech
2016 — 2020
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