Padmini Prakash
Dft Engineer @Google
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WORK HISTORY
Dft Engineer @Google
EDUCATION
PES Institute of technology (PESIT)
BE, Electronics and Communication
University of Southern California
Graduate Student(Master's), Electrical Engineering
SKILLS
ABOUT PADMINI PRAKASH
Design-for-Test professional with work experience on technologies from 40-16nm of ASIC/SOC\'s.Worked on all aspects of DFT design implementation and verification on a few thousand to multi-billion transistorPublished a paper on Automatic MBIST Scheduling in RTL to overcome IR drop issues in DTTC, 2019 and presented in CONECCT, 2019Hardware Design Engineer at Intel India, working on all aspects of DFT including MBIST, DFT on emulator, scan stitching, ATPG, Connectivity checks, LINT checks, Power simulationHardware Engineer at Oracle working as Pre-silicon Verification Engineer on ATPG and System Verilog.Internship at Intel Corporation as Pre-Silicon Validation Intern for USB 3.0 on FPGA platform.MS in Electrical Engineering from University of Southern California with GPA of 3.7Software Engineer for 2 years at Infosys Ltd and won Global Team Excellence Award.Undergraduate student from PESIT, Electronics and Communication. GPA 4.0. Specialties: ATPG, SCAN, MBIST, PCIE/DDR/USB TESTING, 1149.1 & 1149.6, SPYGLASS, JASPER, IJTAG.Language skills: System Verilog, Perl, Python, Verilog, VHDL, C++, ShellVISA: H1B Visa and UK Skilled worker Visa (Tier 2)
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