Padmesh Gaonkar
- Role
- Sr Physical Design Timing Engineer at NVIDIA
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Padmesh Gaonkar
Looking for challenging Back-End physical design/timing integration/clocking position…
Experience
Sr Physical Design Timing Engineer
Oct 2016 — Present
Skills
- Very-Large-Scale Integration (Vlsi)
- Clock Distribution
- Application-Specific Integrated Circuits (Asic)
- Soc
- Circuit Design
- Tcl
- Analog Circuit Design
- Clocking
- Rtl Design
- Perl
- Spectre
- Timing Closure
- Lvs
- System on a Chip (Soc)
- Synopsys Tools
- Cadence Virtuoso
- Digital Product Development
- Drc
- Mixed Signal
- Cmos
- High-Speed Digital Design
- Vlsi
- Crosstalk
- Integrated Circuit Design
- Asic
- Synopsys Primetime
- Static Timing Analysis
- Verilog
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