Padmanabha Nikhil Bhimavarapu

About Padmanabha Nikhil Bhimavarapu

I’m a Design Verification Engineer with 3+ years of experience in SoC verification and RTL design, focused on building reliable hardware systems through robust verification methodologies and scalable test environments. My work centers on ensuring silicon works correctly before tape-out, combining strong technical foundations with systematic debugging and automation. Currently, I work on AXI-based controller verification, where I design UVM-based verification environments using SystemVerilog to validate complex protocol interactions and datapath logic. By implementing assertion-based verification and structured stimulus generation, I’ve helped uncover 9 functional issues before subsystem integration, preventing costly downstream design fixes. I’ve also executed 60+ simulation runs and 40+ directed and random test scenarios, strengthening functional coverage across critical control paths. Beyond verification, my experience includes RTL design and microarchitecture implementation. Earlier in my career, I developed 11 synthesizable RTL modules for communication control logic and collaborated with backend teams to achieve timing closure across 7 datapath processing blocks. I’ve also resolved 12 critical setup and hold timing violations through detailed timing analysis and optimization using industry-standard tools. I enjoy working at the intersection of design, verification, and computer architecture, where understanding system-level behavior leads to stronger hardware validation strategies. My technical toolkit includes: • Verification: UVM, SystemVerilog, SVA, Functional Coverage, Assertion-Based Verification • RTL Design: Verilog, VHDL, FSM Design, Clock Domain Crossing (CDC) • EDA Tools: Synopsys VCS, Verdi, ModelSim, Cadence Xcelium • Synthesis & Timing: Synopsys Design Compiler, PrimeTime, Cadence Genus • Programming & Automation: Python, Tcl, Shell scripting, C/C++ • Architecture: RISC-V, superscalar processors, parallel computing, GPU systems I’m particularly interested in scalable verification methodologies for complex SoCs, where automation, protocol validation, and architectural understanding combine to improve silicon reliability and development efficiency. Long term, I aim to contribute to building high-performance compute systems and next-generation processors, working on verification strategies that enable faster, more reliable hardware development. If you\'re working on SoC verification, computer architecture, or high-performance hardware systems, I’d be happy to connect and exchange ideas.

Experience

1. Design Verification Engineer

   HCLTech

   Aug 2025 — Present · US

   Formulated a UVM verification environment using SystemVerilog, reviewing design specifications with RTL and architecture teams and validating 4 protocol controller modules while uncovering 9 functional issues before subsystem integration- Orchestrated stimulus generation using UVM sequence libraries, clarifying interface behavior with microarchitecture engineers and executing 46 directed and random test scenarios covering AXI transaction handling paths- Instituted protocol rule checks through SystemVerilog Assertions (SVA), coordinating verification checkpoints with senior DV engineers and detecting 6 synchronization violations during simulation validation cycles- Simulated pre-silicon functionality using Synopsys VCS, performing joint debug analysis with design teams and completing 62 simulation runs validating control logic and arbitration blocks- Automated regression execution using Python scripts and VCS simulation logs, coordinating nightly validation cycles with integration engineers and processing 38 regression runs supporting subsystem build verification- Traced signal transitions using Verdi waveform debugging, leading debug reviews with subsystem engineers and isolating 5 protocol timing defects identified during block-level integration testing.

Education

• Indian Institute of Information Technology Design & Manufacturing, Kurnool

  BTech - Bachelor of Technology, Electronics and Communications Engineering

• North Carolina State University

  Master of Science - MS, Electrical and Computer Engineering