Paddy Mamtora

About Paddy Mamtora

Results oriented, highly focused, & committed Senior technical leader with 25+ years of experience in IC design and EDA, mostly in customer facing roles. • Consistently delivered best-in-class power, performance, and area (PPA) solutions for the next-generation Arm cores, by leveraging strategic ecosystem partnerships with Arm & its top customers and collaborating with R&D to develop innovative differentiated technologies.• Multiple years of expertise in leading several WW cross-functional taskforces of experts to deliver differentiated value to our top tier customers• Hands-on expertise in the Digital Implementation and Signoff products with a broad understanding of the Digital, Analog, Mixed-Signal flows and AI/ML solutions• Driver of scalability and deployability programs within the Digital and Signoff Business Group leading to improved productivity and higher customer satisfactionSome aspects of my Arm/Arm ecosystem journey are covered in this blog: https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/paddy

Experience

1. Sr Group Director, Product Engineering

   Cadence

   Jun 1996 — Present · San Jose, CA, US

   Lead for the Digital High-Performance Center of Excellence Team, responsible for keeping Cadence’s leadership position on advanced nodes Arm CPU cores, by delivering the best in class Power, Performance, Area (PPA) in the shortest time• Drove cross-functional OneTeam, that resulted in Cadence Implementation share among WW top semis to change from <10% to 90+% for CPU implementations, and making $300+M positive business impact• Built strong, trust-based relationship at multiple levels (Engineer, Manager, and Executive), making Arm + Cadence an industry benchmark on joint collaboration• Enabled the Arm and Cadence ecosystem partners to jumpstart their implementation by leveraging joint RAKs (Rapid Adoption Kits) and reduce design cycle time by 3-6 months• Wrote, co-authored, delivered tens of papers with Arm, highlighting the fastest time to market implementation solutions on high perf Arm cores• Lead and champion the exec-driven initiative for Deployability within Cadence. • Enhance field and PE productivity by higher efficiency interactions. high quality knowledge transfer, early access/ code bash program, and superior customer support experience for customers• Led the full flow customer driven R&D teams for strategic customers and key regions including Geography customers (which accounted for 60+% of run-rate for the BU) • Led the product engineering teams for the Electrical Signoff products, IREM Analog products

Education

• University of Cincinnati

  M.S., Electrical and Computer Engineering

  1989 — 1992

• University of Mumbai

  B.E., Electroniics Engineering

  1983 — 1988

Skills

• Fpga
• Asic
• Physical Design
• Mixed Signal
• Verilog
• Low-Power Design
• Semiconductors
• Self-Confidence
• Soc
• Perl
• Eda
• Static Timing Analysis
• System on a Chip (Soc)
• Signal Integrity
• Rtl Design
• Vlsi
• Cadence
• Ic
• Timing Closure
• Application-Specific Integrated Circuits (Asic)
• Tcl
• Analog
• Functional Verification
• Integrated Circuit Design