Suresh Pachha
SOC Design Engineeer
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Suresh Pachha
Physical implementation from RTL to GDS including Synthesis, PnR, timing closure and physical verification – Full Chip/SubSystem Synthesis, DP, Block closure, integration & physical verification – Full Chip/SubSystem constraints development, IO budgeting & timing closure – High speed clock tree/mesh planning, distribution, methodology & skew analysis – Experience in various technology nodes (65nm 7nm) with successful tape-out of multiple high-speed/low-power microprocessors.
Experience
Soc Design Engineer
Nov 2016 — Present · Bengaluru, IN
Education
Acharya Nagarjuna University
B.Tech, EEE
2002 — 2006
Vellore Institute of Technology
M.Tech, Vlsi Design
2006 — 2008
Skills
- Asic
- Floorplanning
- Lvs
- Vlsi
- Drc
- Timing Closure
- Physical Verification
- Soc
- Logic Synthesis
- Power Analysis
- Static Timing Analysis
- Physical Design
- Formal Verification
- Primetime
- Clock Tree Synthesis
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