Pablo Pereira Pires
Principal Engineer @Arm
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WORK HISTORY
Principal Engineer @Arm
Cambridge, GB
EDUCATION
Universidade do Vale do Itajaí
Bachelor, Computer Science
SKILLS
ABOUT PABLO PEREIRA PIRES
Computer scientist involved in research in digital systems design since undergraduate. Currently works in functional verification, mainly, metric-driven verification methodologies, verification plan and test cases specification and in the development of self-checking, reusable and automated verification environments.Main goals are to build robust and intelligent verification infrastructures in order to be able to deliver high-quality IP within the project constraints.Main interests are functional verification, digital systems design, computer organization and architecture, project management and Networks-on-Chip (NoCs).Specialties:Programming Languages: SystemVerilog, Verilog, VHDL and Perl.Development tools: git, SVNVerification Related Specialties: verification planning, test cases specification, testbench architecture and design, OVM/UVM, TLM, pseudo-random stimuli generation, functional coverage, assertions (SVA), bug tracking and gate-level simulation.EDA Related Specialties: Cadence, Mentor and Synopsys verification related tools. Altera Quartus II and Mentor ModelSim used for Altera FPGAs prototyping.
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