Paavan Phanindra Rallapalli

Senior Verification Engineer @NVIDIA

Hyderabad, TG, IN
MOBILE NUMBERS
+91 *********19

Signup · Get unlimited contacts

WORK HISTORY

May 2016 — Present

Senior Verification Engineer @NVIDIA

View department →

Ethernet : MACSEC Unit Verification.• Ethernet : Ethernet VIP Development from Scratch: Handled MAC, Macsec Layers and VIP Architecture for Vendor independence, Reusability and Deployment. • LSIO (SDMMC, PWM, TACH, UART, etc): Unit Verification (Frozen IPs), SOC Verification, FPGA and Silicon Validation for all LSIO IPs.• LSIO: SDMMC [SD4.0 to SD7.0 (SDPCIE), SDIO, eMMC] Unit Verification, SOC Verification, FPGA and Silicon Validation Owner.• Worked on 5 Projects o Ethernet Macsec : Part of a 2 Members team.o VIP Development : Part of a 5 Members team. o LSIO : Part of a 2 Members team. o SDMMC : Part of a 2 Members team for 1 Project, and Complete Ownership for next 2 Projects.

EDUCATION

2011 — 2013

Indian Institute of Technology, Delhi

Master of Technology (M.Tech.), Integrated Circuit Design

SKILLS

SocDebuggingCadUvmProcess EngineeringC++AsicXilinxSystemverilogLinuxProcessorsSystem VerificationVlsi CadIntegrated Circuit DesignVhdlSimulationsMicrosoft OfficeVlsiVerilogMatlabArmRtl DesignCProgrammingPerlFunctional VerificationCadence Virtuoso

ABOUT PAAVAN PHANINDRA RALLAPALLI

With over 10 years of experience in verification engineering, I am a passionate and dedicated professional who strives to deliver high-quality and reliable solutions for complex and challenging digital design problems. I have extensive knowledge and skills in SV/UVM across Unit, SoC, Silicon Validation of Low Speed IOs and VIP/Unit Verification of some Ethernet Technologies; with a past work experience on Processor Sub-systems, ARM, Memory, AMBA Protocols.Currently, I work as a Senior Verification Engineer at NVIDIA, where I have successfully handled multiple projects involving LSIOs, SDMMC, Ethernet and MACSEC verification. As a Team, I have also developed an Ethernet VIP from scratch, demonstrating my creativity and innovation. I enjoy working with a talented and diverse team, and I always seek to learn new things and improve my performance. My goal is to contribute to the advancement and excellence of my Team, and Company’s Vision.

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.

Paavan Phanindra Rallapalli — Senior Verification Engineer at NVIDIA in Hyderabad, TG, IN | Unifers