P Pavan Kalyan
layout design engineer
- Role
- Layout Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About P Pavan Kalyan
working as layout design engineer-memory layout worked on HRF compilers in 7nm, ecos and other flows such as lvs drc and other bundle flowsdesigned various layouts for compilers in memories in 5nm various physical verification flows such as lvs,drc
Experience
Layout Design Engineer
Apr 2024 — Present · Bengaluru, IN
Education
Keshav memorial institute
Bachelor of Technology - BTech, electronics and communication
2017 — 2021
Jawaharlal Nehru Technological University
Bachelor of Technology - BTech, Electronics and communication
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