P Mahith Reddy
Design Verification Engineer @Tech M
- Role
- Design Verification Engineer at Tech Mahindra
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About P Mahith Reddy
Welcome to my LinkedIn profile! I am currently working as a Design verification engineer in TechM.Very Large Scale Integration (VLSI) plays a pivotal role in the semiconductor industry and has made significant contributions to its advancement over the years. I would like to contribute to this industry with my acquired knowledge and skill set till now.Skills & Expertise :>Verilog>System Verilog>Universal Verification Methodology(UVM)>System Verilog Assertions(SVA)Hands-On Experience :Description : The IFS_E2E is a RISC-V based SOC level chip which has neorv32core CPU with interfaces like I2C,GPIO,XIRQ,SPI and UART and WDT for Timer, andmemories like IMEM and DMEM.Responsibilities :To Develop the test bench environment for GPIO(General purpose input output)using UVM.Developed SystemVerilog covergroups and coverpoints to monitor the functionalityof GPIO.
Experience
Design Verification Engineer
Apr 2024 — Present
Education
VIT_Vellore Institute of Technology
Bachelor of Technology - BTech
2019 — 2023
Narayana Junior College - India
Intermediate
2017 — 2019
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