Oviya Ramasamy
SoC physical design engineer - electrical analysis
- Role
- Soc Physical Design Engineer - Electrical Analysis at Apple
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Oviya Ramasamy
SOC physical design electrical analysis engineer at AppleSpecialties: Cadence design suite ( netlister, virtuoso, simulator), VHDL, Verilog, Xilinx FPGA, Matlab, Agilent( ADS), Cadence Encounter, Synopsys ICC, Synopsys StarRC, Mentor Graphics Calibre, Micromagic MAX, Ansys Redhawk-SC, Ansys redhawk, Cadence Voltus
Experience
Soc Physical Design Engineer - Electrical Analysis
Oct 2024 — Present · Austin, TX, US
Education
University of Florida
MS, Electrical and Computer Engineering
2011 — 2013
Panimalar Engineering College, Anna University
Bachelor of Engineering, Electrical and Electronics
2007 — 2011
Skills
- Artisan Memory Compilers
- Simplescalar
- Fpga
- Asic
- Computer Architecture
- Rf Circuits
- Eda Tools
- C++
- Drc
- Soc
- Simple Scalar
- Icc
- Excel
- Eclipse
- Syscalc
- Semiconductors
- Spice
- Xilinx Ise
- C
- Vhdl
- Verilog
- Matlab
- Micromagic Sue
- Wattch Simulator
- Agilent Ads
- Lvs
- Calibre
- Microsoft Office
- Vlsi
- Perl
- Cadence Virtuoso
- Micromagic Max
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