Onkar Dhaigude
CPU Design Verification Engineer @MIPS | RISC-V | UVM/SystemVerilog | Ex-Cadence Tensilica | MS NCSU CE ’26 | B.Tech COEP E&TC ’20 | Experineced in CPU/GPU architecture and RISCV | Open to Full-Time Roles
- Role
- Intern at MIPS
- Location
- Raleigh, NC, US
- LinkedIn followers
- 500 followers
About Onkar Dhaigude
I am a CPU Design Verification Engineer with a deep interest in computer architecture and microarchitecture. I enjoy understanding processors at a fundamental level, from ISA behavior to pipeline design and system interactions. My approach to debugging and verification is rooted in architectural clarity. I prefer understanding why something breaks rather than just fixing what breaks.I currently work in CPU DV at MIPS and previously gained valuable experience at Cadence Tensilica. Through this work, I have developed strong exposure to real processor verification environments. I also have solid understanding and practical exposure to the RISC-V architecture and believe I can confidently analyze and solve architectural issues in RISC V based systems.Beyond CPUs, I have a strong interest in GPU architectures and parallel computing. I am genuinely curious about how modern GPUs are structured and optimized, and I continuously work to strengthen my knowledge in that space.I have experience with UVM and SystemVerilog and understand functional coverage and assertion driven verification techniques. While I am comfortable working in SoC verification environments, I am more inclined toward architecture focused roles involving CPU microarchitecture, ISA reasoning, performance modeling, and RTL level thinking.I have a good understanding of protocols such as AXI and I2C, and I am currently learning more about CHI and PCIe. My coursework at North Carolina State University has strengthened my foundation in computer architecture, performance modeling, RTL design, and verification, giving me the confidence to apply for roles in performance modeling, RTL, and advanced DV.I am someone who takes ownership and gets things done. I approach problems methodically, enjoy deep technical debugging, and make effective use of AI tools to accelerate problem solving and analysis. I believe strong fundamentals combined with intelligent use of AI can significantly improve engineering productivity.
Experience
Intern
Jan 2026 — Present · Dallas, TX, US
Education
Dr. D. Y. Patil Vidyapeeth
SSC
2003 — 2014
North Carolina State University
Master of Science - MS, Computer Engineering
COEP Technological University
Bachelor of Technology, Electronics and Telecommunication
Laxmanrao Apte Junior College
HSC, Science
2014 — 2016
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