Onkar Desai

Sr Principal Design Engineer, Tensilica IP

Role: Sr Principal Design Engineer at Cadence
Location: Pune, MH, IN
LinkedIn followers: 500 followers

EngineeringView LinkedIn profile

Experience

Sr Principal Design Engineer
Cadence
Jan 2026 — Present · Pune, IN
RTL Design for L2 Cache controller

Education

St. Francis Institute Of Technology
Bachelor's Degree, Electronics and Telecommunications Engineering
2006 — 2010
Indian Institute of Technology, Bombay
Master of Technology (M.Tech.), Electronic Systems
2013 — 2016

Skills

Opencv
Siebel 7.x
Pl/Sql
R
Xml
Ni Labview
Embedded Systems
Embedded Linux
Web Services
Sql
Python
Oracle
Microcontrollers
C
Matlab
Gnu Radio

Contact information

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Work email
•••••@cadence.com
Personal email
•••••@•••••.com
Direct dial
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Current company

Cadence Design Systems

Software Development · 12K employees · San Jose, California, United States

Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.

cadence.com

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Experience

Sr Principal Design Engineer

Education

St. Francis Institute Of Technology

Indian Institute of Technology, Bombay

Skills

Find verified contacts for anyone on LinkedIn