Omkar Kachare

About Omkar Kachare

I have six years of experience in fault isolation, failure analysis, and reliability enhancement for chipsets, SoCs, and packages. I debug the latest technology node process in the industry to enable testchips and support qualification and field failures, collaborating with a cross-functional team of engineers, designers, to provide root-cause analysis for product quality and reliability issues. I also support design, product engineering, and development activities. I am proficient in CAD/EDA tools such as Sysnav, Allegro, & Avalon.My core competencies include debug, digital, analog and mixed-signal IC design, IC fabrication & process integration, semiconductor characterization & testing. I hold a Master\'s degree in Electronic & Electrical Engineering from California State University, Sacramento, where I focused on micro-architecture design. I excelled in courses such as Advanced Timing Analysis, Analog & Mixed Signal Integrated Circuit Design, Micro-Computer System Design, Advanced Topics in Logic Design, Digital Integrated Circuit Design and Hierarchical Digital Design Methodology. For my Master\'s project, I collaborated with Intel on the failure analysis of USB design, studying the robustness of the IP. During my coursework, I leveraged my leanings to design, verify, and validate multiple circuits using Verilog. I also possess a deep understanding of CMOS design and device physics.I have demonstrated a strong understanding of ASIC Design flow, mixed-signal design, testing & characterization, CMOS fabrication and integration, and failure analysis. I leverage my technical skills, domain expertise, and leadership traits to deliver innovative and impactful solutions for my team and organization.Responsibilities:FIFA support on latest process technologies (2nm, GAA, Backside Power Delivery) testchips.Perform FI & FA on SoC and I/O silicon, addressing issues like electrical over-stress, ESD, and I/O failures during product qualification & field failures.Diagnose and Debug SCAN-related failures (ATPG, SCAN Chain, at-speed) using the Tessent toolset.Experimentation & Research: Design and conduct experiments on Advantest testers, including debug pattern conversions, scripting, CAD, and circuit analysis.Support/ request physical failure analysis using SEM, TEM, nano-probing, 3D X-rays, etc, to isolate issues like transistor degradation, FIN damage, and metal bridging.Key Achievements:Successfully isolated fail mechanisms, including transistor degradation, FIN damage/weak fins, via damage, design debug, shorts/opens, metal bridging, etc.

Experience

1. Silicon Product Failure Analysis Engineer & Component Debug Engineer

   Intel

   Dec 2024 — Present · Hillsboro, OR, US

   Support Silicon Fault Isolation and Failure Analysis on cutting edge processes:Conduct fault isolation and failure analysis for SoC and IO silicon during product qualification and field failures. Address parametric and functional fail modes, including electrical overstress, ESD, reset failures, leakage, no-boot issues, and I/O failures.Ownership of SCAN-Related Failures:Execute and manage SCAN-related failures, including SCAN ATPG, SCAN Chain, and at-speed failures. Utilize the Tessent toolset for diagnosis execution and management.Experiment Design and Research:Design and conduct experiments on testers, such as Advantest testers.Perform debug pattern conversions, basic scripting, CAD analysis, and circuit analysis.Physical Failure Analysis:Handle requests for physical failure analysis, including SEM, TEM, X-sections, nano-probing, 3D X-rays, EBAC, EBIC, EBIRCH, etc. Successfully isolate fail mechanisms such as device degradation, FIN damage/weak fins, via damage, design debug, shorts/opens, and metal bridging. Key Achievements • Successfully isolated fail mechanisms, including transistor degradation, FIN damage/weak fins, via damage, design debug, shorts/opens, metal bridging, etc.Skills: Speed Path Debug · Laser Time Modulation · Communication · Failure Analysis · Analytical Instruments · Oral Communication · Root Cause · Device Characterization · Debugging · Analog Semiconductors

Education

• California State University-Sacramento

  Master of Science - MS, Electrical and Electronic Engineering

  2018 — 2021

• Vishwakarma Institute of Information Technology

  Bachelor of Engineering - BE, Electrical, Electronics and Telecommunications Engineering

  2013 — 2017