Omesh M.
Silicon Engineer @Meta
- Role
- Asic Silicon Engineer at Meta
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Omesh M.
Full Chip Physical Verification,EMIR & Block Physical Design (SYN-GDSII) execution. Tapeout experience for 3nm,7nm,8nm, 12nm TSMC, Samsung & Intel Foundry.
Experience
Asic Silicon Engineer
Dec 2025 — Present
Education
Yeshwant Mahavidyalaya Nanded
Higher Secondary School Certificate, Computer Science
2005 — 2006
VIT University
Master of Technology (MTech), VLSI design
2012 — 2014
Sinhgad Academy of Engineering, Pune
Bachelor's degree, Electrical, Electronics and Communications Engineering
2007 — 2011
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