N V Prajwal

About N V Prajwal

I am an experienced professional with a strong background in SOC (System on Chip) verification, specializing in System Verilog and UVM methodology. Currently working at Tech Mahindra Cerium in Bangalore, Karnataka, I have successfully contributed to multiple projects, demonstrating my expertise in IP verification and documentation.At Tech Mahindra Cerium, I worked on the FED_IP_SHIP_CHIPLET_SOW project from March 2022 to June 2022. My responsibilities included verifying IP\'s based on the test plan, such as axi4-st, axi4-mm, and ca (Channel Alignment). I gained a deep understanding of Axi-st and SPI protocols, ran regressions, improved code coverage in collaboration with the design team, and maintained thorough documentation.In the IFS_ARM_PCOE project from June 2022 to October 2022, I focused on verifying IP\'s including flexray and I2S. I analyzed regression errors, debugged issues, and ensured comprehensive documentation. I also delved into the I2S Spec document, gaining a thorough understanding of the specifications.During my most recent project, MCDMA_QIP, spanning from November 2022 to May 2023, I reduced logfile size, analyzed regression errors, and debugged issues. I utilized the Eclipse-DVT tool and scripting for code alignment.In addition to my project experience, I possess strengths in Analog Electronics, Digital Electronics, CMOS Process, and Basic Electronics. I am proficient in operating systems like Linux and programming languages such as C and Perl. My HVL language expertise includes System Verilog and UVM. I am also skilled in using tools such as Dve, Verdi, and Eclipse-DVT to enhance my productivity and efficiency in the verification process.I hold a Bachelor of Engineering (ECE) from Canara Engineering College, Mangalore, KarnatakaTo further enhance my skills and stay updated with industry standards, I have obtained certifications in UVM and DV Debug from Cerium Systems in December 2021, as well as System Verilog from Cerium Systems in October 2021.I am passionate about delivering high-quality verification solutions and collaborating with cross-functional teams for successful project outcomes. With my strong technical background and dedication to excellence, I am committed to contributing to the growth and success of future projects in the field of SOC verification.Feel free to connect with me to discuss opportunities or explore collaborations related to SOC verification and IP verification.

Experience

1. Design Verifiction Intern

   AMD

   Jul 2025 — Present · Bengaluru, IN

Education

• MPES SDM

  PUC, PCME

• Canara Engineering College

  Bachelor of Engineering - BE, Electronics and Communications Engineering

  2017 — 2021

• RNS Vidyaniketan Murdeshwar

  SSLC

• Manipal School of Information Sciences

  ME, VLSI design