Niyati Shah

About Niyati Shah

Hands-on experience with UVM, System Verilog, Verilog, Python.Strong background in digital design, RTL languages, IP Verification and Simulation.Technical Skills: 1. HDL : VHDL,Verilog 2. HVL : SystemVerilog 3. Verification Methodology : UVM 4. IP Verification : Constrained random verification, Coverage driven verification, Functional/Protocol verification, Regression Mechanism 5. Protocols AMBA AXI3/4, APB, MIPI RFFE, BLE. Tools used : Cadence Incisiv, Cadence IMC Synopsys: VCS, Verdi Mentor Graphics: Questasim, Modelsim, Veloce Xilinx: Vivado, ISE Intel (Altera): Quartus.MS coursework:Logic Verification using UVM | SOC Design using System Verilog | Advanced Computer Architecture | Advanced Digital System Design and SynthesisContact:E-mail ID : n••••••••@gmail.com

Experience

1. Fpga Silicon Design Verification Engineer

   Altera

   Jan 2025 — Present

Education

• San José State University

  Master of Science - MS, Electrical Engineering Technologies/Technicians

  2018 — 2020

• Sardar Vallabhbhai Patel Institute of Technology, Vasad (GTU)

  Bachelor of Engineering (B.E.), Electronics and Communications Engineering

  2009 — 2013

• Nirma Institute Of Technology

  Master of Technology (M.Tech.), Embedded Systems

  2014 — 2016

Skills

• Microsoft Word
• Java
• Universal Verification Methodology (Uvm)
• Microcontrollers
• Uvm
• Microsoft Excel
• Powerpoint
• C
• Microsoft Office
• Embedded Systems
• Regression Testing
• Systemverilog
• Matlab
• Functional Verification
• Ncsim
• Vhdl
• Linux
• Assertion Based Verification
• C++