Nitya Maheshwari
Internship Training - Cadence Virtuoso 90nm @Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore
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WORK HISTORY
Internship Training - Cadence Virtuoso 90nm @Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore
Indore, IN
CMOS Circuit Design: Designed and simulated logic circuits like universal gates, half adders, and multiplexers using schematic entry in Virtuoso.Symbol Creation: Created custom symbols for digital blocks to enable hierarchical and modular design.Testbench Development: Built and applied testbenches for verifying functionality using transient simulations.Layout Design: Created physical layouts of digital circuits, following 90nm design rules.Design Rule Check (DRC): Performed DRC to ensure layouts complied with the technology node’s design constraints.Layout vs Schematic (LVS) Check: Verified electrical and topological equivalence between layout and schematic.Parasitic Extraction (RCX): Extracted parasitics from layout for accurate post-layout simulations.Post-Layout Simulation: Ran simulations using extracted views to validate real-time performance including delays and signal integrity.GDSII Generation: Exported final layout files in GDSII format for fabrication readiness.
EDUCATION
Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore
Electronic and communication with Internet of Thing , Internet of Thing
Lokmanya Tilak Vidhya Vihar Higher Secondary School
High School Diploma, All Subject | Mathematics | Physics | Chemistry
ABOUT NITYA MAHESHWARI
Nitya MaheshwariAspiring VLSI Engineer I am currently pursuing a B.Tech in Electronics and Communication Engineering (2022–2026) at Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore (MP), where I have been developing a strong foundation in electronics, digital systems, and semiconductor fundamentals.My academic and project work is centered around VLSI, digital design, and analog circuit fundamentals, with hands-on experience in CMOS 180 nm and 90 nm technologies using Cadence Virtuoso. I have designed, simulated, and analyzed key building blocks such as 1-bit ALU, SIPO registers or other fundamental block.Along side analog and circuit-level work, I have actively worked on digital coding and FPGA-based design, using tools such as Quartus Prime, Vivado, and ModelSim for RTL development, simulation, and synthesis. I have also explored RISC-V architecture concepts, strengthening my understanding of processor fundamentals, instruction flow, and hardware–software interaction.Currently, during my internship at RRCAT, I am working on a FPGA-based Data Acquisition System, where I am gaining hands-on experience in real-time signal acquisition, digital control logic, and interfacing with precision DACs such as the LTC2662. This project has helped me understand how FPGA logic, communication protocols, and analog interfaces come together in real hardware systems, especially in research and instrumentation environments.Through these experiences, my interests have grown toward analog/mixed-signal design, low-power circuits, custom layout, FPGA-based systems, and semiconductor device behavior, with a strong motivation to work on chip-level and system-level challenges.I am actively seeking internship or research-oriented opportunities where I can further contribute, learn advanced design flows, and grow as a VLSI and semiconductor engineer.
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