Nitin Saxena
Post-Silicon Validation Lead & Engineering Manager at Intel Corporation
- Role
- Post Silicon Validation Lead & Engineering Manager at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Nitin Saxena
Over 16 years of comprehensive experience in Post-Silicon Validation, Analog…
Experience
Post Silicon Validation Lead & Engineering Manager
Jan 2022 — Present · Bengaluru, IN
Education
Manas Sthali public school, bareilly
11th - 12th
2002 — 2004
Dr. A.P.J. Abdul Kalam Technical University
Bachelor of Technology - BTech
2004 — 2008
Skills
- Usb 2.0 Characterization
- Microcontrollers
- Pll
- Cadence Schematic Capture
- Digital Circuit Design
- Microprocessors
- I2c
- Hardware Specification
- Post-Silicon Validation
- Signal Integrity
- Hyperlynx
- Serial Protocols
- Altium Designer
- Pcb Layout Design
- Board Bring-Up
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