Nitin Jaiswal

Experience

1. Principal Engineer

   Qualcomm

   Nov 2011 — Present · Bangalore, IN

   Ownership of Execution & Delivery of the IP Core from planning, front end design to post-silicon verification & debug. Contribution : During this project, Main responsibilities are: 1. Responsible for all Front end Silicon work related to the project which mainly includes: RTL Integration for the next generation IP Sub System. Involved in complete frontend digital ASIC flow, including microarchitecture, design, RTL coding, CDC, linting, synthesis and timing closure 3. Drive innovation to deliver better power, performance and area. Synthesis, STA and netlist delivery for best perf/mm2 and power/mm2. Understanding of the SOC architecture & operation, for each SOC that the IP is integrated. Worldwide integration of innovation & execution, across entire frontend ASIC flow 6. Responsible for CR tracking / Errata management for the derivative products 7. Communication & support to internal & external SW teams. In partnership with PMO, and Silicon team management responsible for Project planning, estimates, scheduling, resources 9. Silicon debug (root cause investigation) using various SW & HW tools, including test fixtures, probes, lab equipment (scopes, logic analyzers), on-chip debug features

Education

• Indian Institute of Technology, Madras

  Master's degree, Electrical and Electronics Engineering

  2000 — 2002

• Indian Institute of Management, Kozhikode

  Executive Post Graduate Diploma in Management

  2011 — 2013

• College of Technology, G.B.Pant University of Agriculture & Technology, Pantanagar, U.P

  Bachelor of Technology (B.Tech.), Electrical and Electronics Engineering

  1996 — 2000