Nitin Gupta

About Nitin Gupta

1 JSSC, 2 ESSCIRC, 1 Electronic Letters Paper Publication.19 Patents related to Clocking and Mixed Signal Circuit DesignHigh Performance LC Oscillators, PLL Design for next-gen Wireline PHYs (Ethernet 112Gbps/224Gbps, PCIe 64/128Gbps). All Digital PLLs, Analog PLL Architecture for wide applications like Automotive, Sensor, Wireline PHYs, NFC, Server & Client Core etc.Extensive experience in Post-Silicon debug and drove several customer SoCs into production quality enabling multi-million dollar revenues for the organization.Proven Leadership Skills, Set up the clocking team in Intel India & within 2 years, the team fully owns differentiated IPs for key Intel SoCs.Key Skills:Phase Locked Loop (PLL), LC & Ring VCO/DCO, Charge Pump, Phase and Frequency Detector (PFD), Time to Digital Converter (TDC), Current & Voltage reference, High Speed & Full Custom Digital Counters, Frequency Synthesizers, & Voltage Regulators, Duty Cycle Sensor/Correctors (DCS/DCC), Tx clocking, Jitter Budgeting, Hybrid PLL Architecture, Digitally Assisted Analog Design

Experience

1. Design Director

   Intel

   Apr 2022 — Present · Bengaluru, IN

   Clocking IP Owner, responsible for high performance LC & RO clocking sub-systems in IP Engineering Group. New Architecture Definition and feasibility study for next generation clocking solutions like Ethernet 112/224Gbps, PCIe6/7 etc. Expertise in external advanced process nodes as well as Intel processes.

Education

• Punjab Engineering College

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2001 — 2005

Skills

• Full Custom Digital Circuit Design
• Analog Circuit Design
• Frequency Synthesizers
• Charge Pump Phase Locked Loop Design
• Pll
• Bandgap References