Nithya D R

About Nithya D R

Experienced VLSI Design Verification Engineer with 4+ years of expertise in validating complex IP designs.Skilled in hardware-firmware co-simulations and UPF-based low-power verification and end-to-end ownership of the verification lifecycle - from planning and strategy to closure.Recognized for strong problem solving, teamwork, and mentoring abilities, along with effective collaboration across global teams.Core Expertise: System Verilog, System Verilog assertions(SVA), UVM, UVM RAL, Functional and Code coverage, VIP integration, Testbench development, Constraint Random Verification, Low power(UPF) verification.Tools : Synopsis VCS, Verdi, QuestasimProtocols: AXI, AHB, APB, Intel IOSF sideband

Experience

1. Design Verification Engineer

   HCLTech

   Sep 2021 — Present · Bengaluru, IN

   Client : Intel TechnologyKey Contributions:Lead end-to-end verification of Power Management Controller IP, using System Verilog, UVM and UPF-based low-power methodologies.Integrated VIPs, built verification components like scoreboard, reference model, response model, data path checkers, assertions, coverage models.Executed standalone hardware validation, hardware-firmware integration, and cross-feature validation.Collaborated with global teams to deliver high-quality, sign-off ready designs within aggressive timelines.Guided and upskilled freshers in verification methodologies, enabling faster ramp-up and improved team efficiency.

Education

• Visvesvaraya Technological University (VTU)

  Bachelor of Engineering - BE

  2016 — 2020