Nithish Devadiga
SOC DFT Engineer @ Intel Corporation
- Role
- System-on-chip Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Nithish Devadiga
9 years experience in DFT implementation, verification and post-silicon validation.Skilled in Tessent MBIST Insertion/Validation, Repair and EFUSE methodology implementation.Automatic Test Pattern Generation (ATPG) and GLS ATPG pattern simulations.Post-Silicon Validation of Structural test Patterns(SCAN) on Verigy 93k Tester, Pattern characterization across PVT corners.
Experience
System-on-chip Design Engineer
Jul 2020 — Present · Bengaluru, IN
SoC DFT Engineer:Currently working in DFT Methodology implementation team on XEON chips. DTF Integration, MBIST Insertion/verification,Repair and Efuse Implementaion/validation.Scan insertion, ATPG pattern generation and simulation.
Skills
- Powerpoint
- Microsoft Excel
- Microsoft Office
- Unix
- Red Hat Linux
- Leadership
- English
- Windows
- C
- C++
- Microsoft Word
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