Nithin Sankar K
Senior Physical Design Timing Engineer @ Intel Corporation | STA - Protocols planning, Constraints Development, Timing convergence/signoff
- Role
- Physical Design Timing Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
Experience
Physical Design Timing Engineer
Jul 2016 — Present · Bengaluru, IN
Timing constraints developmentFunc/Test protocols planningTiming sign-off/convergence for SoC\'s.First Level Manager
Education
Indian Institute of Technology, Bombay
Master of Technology (M.Tech.)
2013 — 2016
St. Thomas college HSS Trichur, kerala
Physics, Chemistry, Mathematics, Computer Science, English, Hindi.
2005 — 2007
College of Engineering, Trivandrum
Bachelor of Technology (B.Tech.)
2007 — 2011
Skills
- Asic
- Microsoft Word
- Python
- Ttcn-3
- Microcontrollers
- Silicon Validation
- Photoshop
- Microsoft Technologies
- Linux
- Rtl Design
- System Integration Testing
- Rf Design
- Rfid Applications
- Matlab
- Cadence Spectre
- Lightroom
- Cadence Virtuoso
- Eagle Pcb
- Analog Circuit Design
- Vhdl
- Programming
- Microsoft Office
- Vlsi
- C++
- Regression Testing
- Microsoft Excel
- Android
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