Nithin S.

Sr Staff Engineer Mgr @Qualcomm

Cambridge, GB

Server CPU Implementation:AUDIO SS / MIXED SIGNAL IP DEV : 14nm tech node,/ 6nm /4nm tech node SS LEAD: Owning (hands on) RTL2GDSII / Roadmap Planning AUDIO SOC: 22nm tech node, SOC 18.8 mm2 Die Area SOC: Owned (hands on) Power Optimization meeting Target Metric AUDIO SOC: 14nm tech node, SOC 18.8 mm2 Die Area PD Lead: overall execution, SOC FP/PNR, planning & technical guidance WIFI SOC: 14nm tech node, SOC 22.5 mm2 Die Area PD Lead: overall execution, SOC FP/PNR, planning & technical guidance WIFI SOC (V2): 28nm technology node, SOC 36.8 mm2 Die Area PD Lead: Improved QoR, Top CTS, Guided LP / Timing / Functional ECO AUDIO SOC: 28nm tech node, SOC 47.5 mm2 Die Area SOC: Owned TOP Partition / FT Planning | FUNC ECO | CLP Clean-up HM: Lead 2M+ instances, 130+ macro DSP CoreHM Lead: Display / Wi-Fi Sub system Lead, 5nm / 14nm tech node 3 HMs within DDR Sub System: 7nm tech node

Manipal Academy of Higher Education

MS VLSI, VLSI CAD

IJHS

ICSE / ISC, Basic Science

Cochin University of Science and Technology

BTech, Electronics & Communication