Nithin Maiya
Senior Director Of Engineering @ Intel Corporation| Post Silicon/Platform Validation | Data Center Systems, AI & Edge | Executive Program Management Columbia Business School
- Role
- Senior Director of Engineering at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Nithin Maiya
Senior engineering leader at Intel with end‑to‑end accountability for silicon and platform validation, driving outcomes from first power‑on through PRQ and customer deployment. I lead large, multi‑disciplinary organizations across pre‑ and post‑silicon domains, aligning engineering execution to business priorities, market windows, and customer adoption signals. My focus is on transforming complex validation into predictable, scalable delivery through operating rigor, data‑driven decision‑making, and automation at scale. I partner closely with architecture, product, and software leaders to balance speed, quality, and cost across the lifecycle. Known for building strong leadership benches and high‑ownership cultures across geographies. Passionate about turning deep technical capability into durable competitive advantage and execution excellence,focusing on strengthening AI and data center platform readiness, Edge-AI, scaling validation strategies that support heterogeneous compute, accelerated workloads, and system‑level performance, power, and reliability. My priority is to enable faster, more predictable adoption of next‑generation AI infrastructure by tightly aligning silicon, platform, and software execution to market and customer demand.
Experience
Senior Director of Engineering
Mar 2026 — Present · Bengaluru, IN
Leading senior engineering execution across silicon/platform validation with accountability for predictable readiness, Quality & Stakeholder alignment across a complex ecosystem,Drive modernization of validation strategy through metrics-driven execution and scalable automation to improve validation quality, debug efficiency, and overall product confidence. Advancing AI and data center platform readiness through segment based, system level validation—aligning heterogeneous compute, memory, and interconnect capabilities with real customer configurations to deliver predictable performance, reliability, and scalable deployment.
Education
Columbia Business School
Executive Program Management
Visvesvaraya Technological University
BE, Electronics & Communication
University of Massachusetts Global
Executive MBA, Business Administration and Management, General
Skills
- Fpga
- Asic
- Static Timing Analysis
- Perl
- Tcl
- Analog
- Eda
- Specman
- Functional Verification
- Debugging
- Amba Ahb
- Vhdl
- Simulations
- Rtl Design
- Ic
- Power Management
- Vlsi
- Dft
- Integrated Circuit Design
- Usb
- Verilog
- Mixed Signal
- Low-Power Design
- Arm
- Semiconductors
- C
- Soc
- Systemverilog
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