Nishtha Ledwani
Lead Design Engineer at Cadence Design Systems
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Nishtha Ledwani
Over 3 years of experience in metric driven constrained Random Verification of Pre-Silicon RTL. Experience in verifying low latency oriented algorithmic Strategy Applications. Skills: HDL: Verilog, System Verilog Methodology: Verilog-UVM, Python-UVM (Cocotb) Scripting Languages: Python, Shell Protocols: 10G Ethernet, AMBA-APB Simulation Tools: Questasim, Aldec Riviera Pro Software Tools: Wireshark, Jenkins, Redmine OS: Linux, Windows
Experience
Lead Design Engineer
Jan 2023 — Present
Education
Rajiv Gandhi Prodyogiki Vishwavidyalaya
Bachelor of Engineering - BE, Electronics and Communication Engineering
2012 — 2016
Gyan Ganga Institute of Technology, Jabalpur
M.Tech, Embedded System and VLSI Design
2017 — 2019
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