Nishant Shah
SOC Design Engineer @ Intel
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Nishant Shah
Chip Integration, Physical Integration / Floorplan, IO Planning, RDL, Bump planning…
Experience
Soc Design Engineer
Jul 2015 — Present · Bengaluru, IN
Chip Integration, Physical Integration / Floorplan, IO Planning, RDL, Bump planning, Hard-IP Integration, Physical Design - Place and Route - Physical Verification and Tape-out.
Skills
- Standard Cell
- Debugging
- Memory Layout
- Cmos
- Verilog
- Pyxis
- Analog
- Digital Electronics
- Eda
- Asic
- Lvs
- Sram
- Drc
- Ic
- Caliber
- Vlsi
- Analog Layout
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