Nishant Potphode
Principal Design Engineer at Cadence Design Systems | ex NXP semiconductor |ex Synopsys |ex Invecas |ex Applied Micro
- Role
- Principal Design Engineer at Cadence
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Nishant Potphode
SERDes PLL(PFD, CP/Dual loop-CP, LPF filters, LC/RC-VCO, Fb/ref div)- Digital PLL - Frequency Doubler- CML dividers- CML to CMOS Converters - AC/DC JTAG, Receiver- RX signal Detector- DFE Latch Calibration
Experience
Principal Design Engineer
Sep 2024 — Present · Hyderabad, IN
Education
Vellore Institute of Technology
Master of Technology (MTech), VLSI Design
2014 — 2016
Skills
- Xilinx Ise
- Html
- Integrated Circuit Design
- Matlab
- Field-Programmable Gate Arrays (Fpga)
- Analog Circuit Design
- Very-Large-Scale Integration (Vlsi)
- Analog Ic Design
- Mixed Signal
- Cmos
- Integrated Circuits (Ic)
- Application-Specific Integrated Circuits (Asic)
- Layout Design
- Microsoft Office
- Vlsi
- Keil
- C
- Fpga
- Asic
- Mixed-Signal Ic Design
- Cadence Assura
- C++
- Simulations
- Linux
- Modelsim
- Ni Multisim
- Cadence
- Verilog
- Rtl Design
- Tcl
- Cadence Spectre
- Perl
- Eda
- Cadence Virtuoso
- Electronics
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