Nishant Patel

About Nishant Patel

11 years of work experience in ASIC/FPGA Verification domain with SV, UVM & OVM testbenches ->Experience in VIP development; SoC+Subsystem level & IP level verification primarily in WLAN-MAC, Ethernet-NIC & Automotive products domain->Good understanding of the ASIC and FPGA design flows->Experience in writing/debugging RTL in Verilog HDL and Testbench development in SystemVerilog/UVM->Very good knowledge in verification methodologies (UVM/OVM)->Good knowledge of Digital Design Concepts->Experience in using industry standard EDA tools for the front-end design and verificationVLSI domain Skills -HDLs : Verilog Scripting Language : PerlHVL : SystemVerilog Verification Methodologies : Coverage Driven Verification, Assertion Based Verification TB Methodology : UVMEDA Tool : Questa, VCS-Verdi, NCsimDomain : ASIC/FPGA Design Flow, Digital Design methodologiesKnowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, ABV

Experience

1. Engineer Staff

   Qualcomm

   Nov 2024 — Present · Bengaluru, IN

Education

• Infocity Junior Science College

  School, PCM(Physics Chemistry Mathematics)

  2008 — 2009

• Ganpat University

  Bachelor of Technology (B.Tech.), Electronics and Communication

  2009 — 2013

Skills

• Matlab
• Linux
• Assertion Based Verification
• Vlsi
• Functional Verification
• Digital Electronics
• Xilinx
• Systemverilog
• Verilog
• Microcontrollers
• Application-Specific Integrated Circuits (Asic)
• Electronics
• Rtl Design
• C
• Uvm
• Xilinx Ise
• System on a Chip (Soc)