Nishant Kumar
Design Verification Trainee | System Verilog | UVM | Functional Coverage | Assertions | Testcases | Regression | Layer Testbench approach | AXI Protocol
- Role
- Design Verification Trainee at Indicus Technology
- Location
- New Delhi, DL, IN
- LinkedIn followers
- 500 followers
About Nishant Kumar
I have successfully completed Certification Training program in Design verification where I have woked extensively on System Verilog, UVM, Functional Coverage, Assertions, Testcases & Regression etc.Following are the projects on which I have worked1. AXI Protocol using UVM methodology (VIP Based Model)- Out of order response, reactive slave agent, pipeline driver Callback support, package, active & passive agent, TLM Port & TLM fifo Exclusive access, functional coverage, assertion, testcases & regression2. RAM verification using System Verilog- Polymorphism, reusable macros & fork-join, mailbox concept. Functional coverage to verify design correctness. Regression testing with randomized and directed testcases. System Verilog Event for the handshaking purpose.3. APB Design and Verification using System Verilog- Polymorphism, reusable macros & fork-join, mailbox concept. Functional coverage to verify design correctness. Regression testing with randomized and directed testcases. System Verilog Event for the handshaking purpose.I am currently seeking opportunities in ASIC / SoC Design Verification, where I can contribute to quality-driven verification, learn from complex designs, and grow as a verification engineer.Alongside verification, I bring 2+ years of industry experience in Technical Support and Pre-Sales at Matrix Comsec, where I worked on system-level debugging, hardware–software integration, customer requirement analysis, and technical presentations.
Experience
Design Verification Trainee
Mar 2025 — Present
Education
Birla Vishvakarma Mahavidyalaya Engineering College, Anand, Gujarat
BE/BTECH, Electronics and Communication Engineering
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