Nishad Patil
Semiconductor Design Enablement
- Role
- Hardware Engineer at Google
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Nishad Patil
As a semiconductor design enablement engineer I apply my expertise in layout design and leading-edge technology development to create and optimize integrated circuits for various applications. I have over 15 years of experience in custom layout design, layout automation flows, process design kit (PDK) architecture, compact modeling, and physical verification for CMOS and silicon photonics technologies.I have a strong background in CMOS device physics, semiconductor fabrication process, layout design rules, and layout dependent effects, which enables me to design high-performance and reliable photonic devices and systems. I am proficient in various layout, simulation, verification, and automation tools, such as Optodesigner, IPKISS, Klayout, gdsfactory, Ansys Lumerical Interconnect, Cadence Virtuoso, Synopsys Custom Compiler, HSPICE, STAR-RC, Calibre, ICV, Shell Scripting, Python, and Cadence SKILL. I am also experienced in characterizing and testing electronic devices using I-V, C-V measurements. My goal is to contribute to the innovation and advancement of semiconductor technologies for applications that improve human life
Experience
Hardware Engineer
Apr 2024 — Present · San Francisco, CA, US
Education
North Carolina State University
MS, Electrical Engineering
2008 — 2010
Visvesvaraya National Institute of Technology
B. Tech, Electrical and Electronics Engineering
2004 — 2008
Skills
- Lvs
- Cadence Virtuoso
- Solid State Physics
- Star-Rc
- Circuit Design
- Hspice
- Device Characterization
- Drc
- Physical Design
- Physical Verification
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