Nischal Raj

About Nischal Raj

Experienced Design Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in System Verilog, Verilog, UVM, OVM, Digital Design and Computer Architecture. Strong engineering professional with a Master\'s Degree in Electrical Engineering (VLSI and Computer Architecture) from University of Southern California. Areas of interest include Pre-Silicon IP verification, Digital design and Computer architecture-Skills-Hardware Description Languages: System Verilog, Verilog and VHDL-Verification methodologies: UVM/OVM-Programming: C, C++, Java, Embedded C,MIPS Assembly-Scripting: Perl,Shell-EDA tools: Synopsys DC, Xilinx ISE, Primetime, Cadence Encounter,Cadence Virtuoso, Cadence Spectre, Chipscope Pro,Digilent Adept-Programming Platforms: Eclipse, AVR Studio, HSpice, ModelSim,Cadence NCSim MATLAB-Specialties:Computer system architecture, ASIC Design, Physical Design, VLSI System Design,Digital Logic Design,Gate Level Simualtion, Schematic and Layout Design, Register Transfer Level (RTL) design and implementation,Design Implementation on FPGA, RTL Simulation, RTL Synthesis/ Debugging, Static Timing Analysis(STA), Testbench Development, Design Verification-Contact: n••••••••@gmail.com

Experience

1. Member of Technical Staff - Design Verification

   AMD

   Nov 2020 — Present · Santa Clara, CA, US

   Responsible for the Pre-Silicon verification of USB IP used as part of South Bridge IO in AMD’s next generation client/server SoC’s. • Involved in the functional verification of different features related to USB2/USB3 and USB4 IP with focus on protocol layer verification, low power, performance related features and compliance testing. • Created test plans and necessary sequences/tests along with developing BFM’s, scoreboards, monitors, assertions and other testbench modules in UVM framework required for feature verification. • Worked closely with Design/Architecture/Firmware teams for bring up of complex features implemented as part of the USB controller and involved in the full-fledged feature verification root causing various failures to Design/DV/FW issues covering all corner cases to achieve a high-quality design. • Responsible for carrying out regular regressions, debugs, coverage analysis for the various features throughout the project cycle and delivering high quality validated IP for multiple projects.

Education

• Sri Jayachamarajendra college of engineering

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2006 — 2010

• University of Southern California

  Master of Science (M.S.), VLSI and Computer Architecture

  2014 — 2016

Skills

• Xilinx
• Java
• Matlab
• Cadence Virtuoso
• Vlsi
• Linux
• Modelsim
• Vhdl
• Simulations
• Debugging
• Computer Architecture
• C
• Testing
• Perl
• Fpga
• Embedded Software
• Asic
• Verilog
• Tcl
• C++