Nisarg Chhaya

Engineer @Arm

Bengaluru, IN

Formal Property Verification• Worked on variety of IPs like Fastpath (CHI prefetch splitter), Address Translation Unit, AXI Address Remapper, DCLS CPU Bridge. Identified multiple bugs during the design bring-up phase.• Managed task planning with investigation from scratch, improvements to legacy setup, developing unified flows for bringing up various configurations of automotive designs & future scalability.• Leveraged Jasper DLH hunting technique & successfully caught multiple corner case deadlock bugs.• Bugs Found: DCLS mode switch bug, lockstep counter timeout error, fault vector propagation, req buffers not empty, data integrity mismatches, deadlocks, CHI REQ protocol violation, Illegal CHI FSM transition during quiescent state etc.Formal CSR Verification• Verified control and status registers of SOC level clock controller using Jasper CSR App.• Did number of improvements in legacy CSR setup like removing overconstraints, developing unified flows, proper documentation and targeting full proof. Delivered fully verified clock control IP post all improvements.Formal Connectivity Verification• Worked on connectivity verification for number of instances of CPU & clock controller IPs.• Imparted formal verification knowledge to the team to improvise connectivity verification flows by including toggle and COI checks into the environment. Helped number of engineers- seniors & juniors during their debug phase.Sequential Equivalence Check• Worked on clock gating verification using Jasper SEC App on CHI prefetch splitter design. Used storage FIFO elements at outputs to cater the variable delay and used Arm LPIQ VIP to cater LPIQ protocol behaviour.

Gujarat Technological University (GTU)

Bachelor of Engineering - BE, Electronics and Communication Engineering

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech, Microelectronics