Nirupam Dutta

About Nirupam Dutta

Nirupam Dutta is a seasoned Analog and Mixed-Signal Circuit Design Engineer with around a decade of experience in developing high-performance analog and mixed-signal integrated circuits. Over the years, he has built a strong portfolio of work across a wide spectrum of circuit blocks, including operational amplifiers (OPAMPs), bandgap reference circuits, phase-locked loops (PLLs), delay-locked loops (DLLs), time-to-digital converters (TDCs), and digital-to-analog converters (DACs). Nirupam\'s in-depth understanding of analog design principles, combined with hands-on experience across multiple technology nodes, has allowed him to deliver robust, low-power, and high-precision solutions for complex system-on-chip (SoC) designs.Currently, Nirupam is contributing to the development of high-speed PLLs operating up to 28 GHz for advanced SerDes applications. His responsibilities include the design and optimization of critical PLL sub-blocks such as voltage regulators, charge pumps, VCOs, and output clock drivers. With experience in both LC-based and ring-based PLL architectures, he ensures optimal trade-offs between jitter performance, power efficiency, and silicon area. Additionally, his background includes working on both transmitter (Tx) and receiver (Rx) front-end circuits, making him a well-rounded contributor in high-speed analog and mixed-signal system design. Nirupam’s deep technical insight, problem-solving abilities, and commitment to innovation continue to drive success in mission-critical design projects.

Experience

1. Analog Design, Staff

   新思科技股份有限公司

   Aug 2022 — Present · Bengaluru, IN

   Designing high-speed PLLs (up to 28GHz) for advanced SerDes applications-Developing critical analog/mixed-signal blocks: VCOs, charge pumps, regulators, and output clocks-Working on both LC and ring oscillator-based PLL architectures-Focused on optimizing performance, power, and area in complex IP designs-Contributing to Tx and Rx front-end circuit design and integration-Engaged in schematic design, simulation, layout review, and silicon validation-Supporting cross-functional collaboration for IP delivery across multiple technology nodes

Education

• National Institute of Technology Jamshedpur

  Master of Technology (M.Tech.), VLSI & EMBEDDED SYSTEM

  2014 — 2016

Skills

• Phase-Locked Loop (Pll)
• Soc
• Physical Design
• Digital Electronics
• Bandgap References
• Perl
• Vhdl
• Tdc
• Verilog
• Adcs
• Dll
• Dac
• Analog Circuit Design
• Mixed-Signal Ic Design
• C++
• Integrated Circuit Design
• Fpga
• Cadence