Nirmalya Ghosh

CEO @Dxcorr Design Inc

San Francisco, CA, US
EMAILS
n•••••••@dxcorr.com
MOBILE NUMBERS
+14•••••••95

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WORK HISTORY

Jan 2010 — Present

CEO @Dxcorr Design Inc

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Sunnyvale, CA, US

DXCorr develops driving edge physical IP arrangements in cutting edge process hubs for an extensive variety of SoC designs incorporating complex memory IP-SRAMs, CAMs, Multiports, memory subsystems, and standard cells.The emergence of mobiles, tablets, smart watches and other similar devices gave prominence to power in ASIC designs. Providing the best PPAL (Power, Performance, Area, and Leakage-key metrics) in the least possible time is the challenge faced by every design house in the VLSI sphere. DXCorr is uniquely equipped to meet this challenge with our highly optimized physical IPs, specific custom blocks, and expert physical design teams. We deliver on even the most demanding specs by developing various in-house tools that push the boundaries of the whole design process. This is driven by a design philosophy that combines the potential of Computer Aided Design with the algorithmic nature of IP development. With in-house software reducing layout generation time and a design team working to provide best PPAL using a suite of optimization analyses to reduce iteration cycles, we deliver best-in-class physical IP solutions across the full range of process nodes. Our advanced Physical IP portfolio offers a comprehensive set of IPs covering Foundation IP blocks such as SRAMs, standard cells and I/Os for most of the building blocks of SoC design, specialized physical IPs -TCAMs, multiport register files, customizable datapath – that helps our customers build highly differentiated products for low power or high performance applications and custom PDK and PCELL development for Mixed Signal IC design.From complex ASIC solutions to hardening of SoC cores, DXCorr offers the highest quality design service, with 200+ top engineers in a global team, enabling our customers achieve significant time-to-market and performance advantage.

EDUCATION

1988 — 1990

Jadavpur University

ME, Computer Engineering

1984 — 1988

Indian Institute of Engineering Science and Technology (IIEST), Shibpur

BE, Electronics and Telecomm. Engg.

SKILLS

SocTimingIpFpgaAsicPre-SalesStrategySemiconductorsVlsiP&L ManagementEdaManagementSignal Integrity

ABOUT NIRMALYA GHOSH

An enterprising and progressive engineering executive with extensive experience in the following areas, • Chip Design • Memory Compiler/ GPIO/ Mixed_Signal/ StdCell development • Methodology/CAD Development • Production Control • Product Management • Resource Management • Ecosystem Management • Executive Management • Corporate ResponsibilitiesLed multi-functional and multi-site teams for developing industry-leading technology products. Created sustainable and scalable engineering operations and product development environment. Promotes teamwork, technical inventiveness, methodology upgrade, customer focus and quality. Invests in an open-door policy to ensure strong communication and understanding of objectives. Contributes to company success through business awareness and self-motivation

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