Nirmaljeet Singh

About Nirmaljeet Singh

20 years of Design Verification Experience using UVM, SystemVerilog, Vera, C, PERL. …

Experience

1. Sr Staff Validation Lead

   Intel

   Jan 2022 — Present · CA, US

   IAmIntelPower Management Control of CPU.• Verification of PMC Next Gen. Architected and Developed various Configurable, Self-Checking Verification Component (VC)/ Agents of PMC Ips with response model, usedin the Next Gen PMC Environment & Test bench development using scalable & configurable techniques. Configurable Auto response modelling toacknowledge design request or triggered by tests & sequences.• Created various PMC sub systems and enabled Synopsys AXI4 to program Master & Slave logic to perform Write & Read functions of Initiator & Target.• Verification of Intel CPU Power Management Controller writing Testplan/ Varification Architecture Specification, Sequence, writing assertions Testcases, Scoreboard & Functional coverage & debugging Regression of Runtime PMC.• Developed LTR scoreboard, monitor Latency from various IPs and create expected snoop/non-snoop QOS messages • Scoreboard developed to verify NDE, PNDE, HPET, TNTE timed events. AMBA q channel features implementation & bring up and verify cross functional protocols. Mentor & Guide team members.• Co-authored DTTC Paper which got selected for publication.

Skills

• System on a Chip (Soc)
• Soc
• Universal Verification Methodology (Uvm)
• C++
• Testing
• Uvm
• Asic
• Computer Architecture
• Rtl Coding
• Perl
• Ethernet
• Vhdl
• Logic Synthesis
• Pcie
• Verilog
• Debugging
• Hardware
• Systemverilog
• C
• Functional Verification