Nipun Naina
Senior Principal Design Engineer at NXP Semiconductors
- Role
- Senior Principal Design Engineer at NXP Semiconductors
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Nipun Naina
Senior Principal Design Engineer with around 18+ years of experience in SOC/FPGA RTL design• Hardware functional / Security/ Safety requirement Gathering• SOC design• RTL design, micro-arch Design• VHDL, Verliog, System Verilog• Synthesis & Timing checks• ARM protocols – AXI,AHB,APB• ARM- Interconnects -NIC & AHB based Crossbar• ARTERIS NOC• ISO 26262 based SOC• DMA• HDMI transmitter and receiver.• HSSL, SIPI, SPI, I2C, UART.• RSDS transmitter and receiver.• Open LDI transmitter and receiver• Fuses and fuse controller TAPNW• AI based algorithms
Experience
Senior Principal Design Engineer
May 2022 — Present
Education
Kurukshetra University
Bachelor of Technology (B.Tech.), Computer Science and Engineering
2000 — 2004
Centre for Development of Advanced Computing (C-DAC), Mohali
Master of Technology (M.Tech.), VLSI Design
2004 — 2006
Skills
- Modelsim
- Field-Programmable Gate Arrays (Fpga)
- Altera
- Vhdl
- Rtl Design
- Digital Ic Design
- Xilinx
- Electronics
- Chipscope Pro
- Application-Specific Integrated Circuits (Asic)
- Verilog
- Microsoft Office
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