Nimish S.

About Nimish S.

Summary• Highly experienced engineering leader with strong technical as well as leadership skills.• Currently leading four motivated teams at Samsung Semiconductors India Research (SSIR) to design and validate cutting edge SSD solutions.• Quality focused with a habit of pursuing depth in any field I work on. • B.Tech (EE) from IIT, MS (EE) from UTA, 14 years of work experience at LSI/Avago/Broadcom in Minneapolis, USA. SSIR, Bengaluru, India (2024 - Present)• Circuit Team: Design and validate PCB for various SSD solutions• Host-Interface Team: Simulate and validate Host interface (USB, PCIe, SATA, etc) signal integrity (SI)• Memory-Interface Team: Simulate and validate Memory interface SI (Controller to NAND/DRAM)• EMC Team: Simulate and validate EMC for various SSD solutionsBroadcom, Minneapolis, USA (20••••24)Product Lead• Led two teams across US and China to drive huge validation efforts within a tight timeline• Identify future needs and gaps in current test platform• Determine risk and readiness for upcoming projectsValidation • Analog validation of preamp (PA) chips used in hard drives. • Made high quality validation plans that involved over 500 different tests • Led to zero validation escapes for most of the projectsHardware • Designed 4 to 8 layer high-speed, high SI impedance controlled PCBs required for validation (~20GHz) • Introduced several PCB checklist items to reduce human errors and speed up the layout • Reduced hardware spending by consolidating several PCBs into one with acceptable SI Debug • Develop custom tests to help find root cause or recreate issues without customer hardware • Customer interfacing for several high priority debug issuesSkillsValidation/Hardware: • Tektronix/Keysight oscilloscopes, data generators, BERTs, AWGs, spectrum analyzers, network analyzers, Keithley multimeters, source-meters. • Pretty good coder – language no bar. • C/C++, MATLAB, Excel, VB, Python, Labview, Test-Stand. • Excellent reporting skills using PowerPoint and data analysis using Excel. • Cadence Allegro for board design/layout. Modeling • ADS multilayer model, dynamic link, SnP parameters, RFIP modeling. • ANSYS Mechanical, Design Modeler for thermal analysis.Mixed-Signal IC Design (School level and internship at Texas Instruments, India) • Cadence: ICFB, Virtuoso-Schematic, ADE (Spectre & HSPICE), Verilog, C/C++.

Experience

1. Associate Director

   Samsung Semiconductor

   Oct 2024 — Present · Bengaluru, IN

Education

• The University of Texas at Arlington

  MS, Electrical Engineering

  2007 — 2009

• Indian Institute of Technology (Indian School of Mines), Dhanbad

  B.Tech., Electronics Engineering

  2003 — 2007

Skills

• Circuit Design
• Vlsi
• Integrated Circuit Design
• Verilog
• Network Analyzer
• Oscilloscope
• Debugging
• Lvs
• Cadence
• Ic
• Testing
• Soc
• Analog
• Spectrum Analyzer
• Analog Circuit Design
• Labview
• Asic
• Pll
• Semiconductors